| CPC H10K 59/131 (2023.02) [H10K 59/1213 (2023.02)] | 9 Claims |
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1. A display device comprising:
a pixel circuit provided corresponding to a data line and a scanning line, wherein
the pixel circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a display element,
the first transistor supplies a current in accordance with a voltage between a gate node of the first transistor and a source node of the first transistor to the display element via the fourth transistor,
the second transistor is disposed between the data line and the gate node of the first transistor and is turned on or off in accordance with a potential of the scanning line,
the third transistor is disposed between the data line and a drain node of the first transistor,
the fourth transistor is disposed between the drain node of the first transistor and the display element, wherein
in a first period, the second transistor is on state, the third transistor and the fourth transistor are off state, and a voltage that turns on the first transistor is applied to the gate node of the first transistor via the data line,
in a second period after the first period, the second transistor and the third transistor are on state, and the fourth transistor is off state, and
in a third period after the second period, the second transistor is on state, the third transistor and the fourth transistor are off state, and a data signal having a voltage in accordance with a current flowing to the display element is supplied to the data line.
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