US 11,751,433 B2
Transistor display panel including lower electrode disposed under a semiconductor and display device including the same
Hyuk Soon Kwon, Asan-si (KR)
Assigned to Samsung Display Co., Ltd., Yongin-Si (KR)
Filed by Samsung Display Co., Ltd., Yongin-Si (KR)
Filed on Apr. 8, 2021, as Appl. No. 17/225,174.
Application 17/225,174 is a continuation of application No. 16/686,033, filed on Nov. 15, 2019, granted, now 10,991,784.
Application 16/686,033 is a continuation of application No. 15/481,273, filed on Apr. 6, 2017, granted, now 10,483,340, issued on Nov. 19, 2019.
Claims priority of application No. 10-2016-0042782 (KR), filed on Apr. 7, 2016.
Prior Publication US 2021/0225977 A1, Jul. 22, 2021
Int. Cl. H10K 59/121 (2023.01); H01L 27/12 (2006.01); H10K 59/131 (2023.01); H10K 71/00 (2023.01)
CPC H10K 59/1213 (2023.02) [H01L 27/1214 (2013.01); H10K 59/131 (2023.02); H10K 71/00 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A transistor display panel comprising:
a substrate;
a lower electrode disposed on the substrate;
a buffer layer covering the lower electrode;
a transistor disposed on the substrate; and
a pixel electrode connected to the transistor,
wherein the transistor includes:
a semiconductor on the substrate,
a first insulating layer disposed on the semiconductor,
a gate electrode on the first insulating layer overlapping the semiconductor,
a second insulating layer covering the gate electrode, and
a source electrode and a drain electrode disposed on the second insulating layer,
wherein the lower electrode is disposed under the semiconductor and is electrically connected to the pixel electrode,
wherein the semiconductor includes a channel, and a source region and a drain region disposed at respective sides of the channel, and
wherein the source region and the drain region are respectively connected to the source electrode and the drain electrode.