US 11,751,409 B2
Semiconductor device
Tomoaki Atsumi, Kanagawa (JP); Shuhei Nagatsuka, Kanagawa (JP); Tamae Moriwaka, Kanagawa (JP); and Yuta Endo, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Sep. 3, 2021, as Appl. No. 17/466,442.
Application 17/466,442 is a continuation of application No. 16/810,902, filed on Mar. 6, 2020, granted, now 11,114,449.
Application 16/810,902 is a continuation of application No. 16/275,380, filed on Feb. 14, 2019, granted, now 10,593,683, issued on Mar. 17, 2020.
Application 16/275,380 is a continuation of application No. 15/591,150, filed on May 10, 2017, granted, now 10,217,752, issued on Feb. 26, 2019.
Application 15/591,150 is a continuation of application No. 14/637,542, filed on Mar. 4, 2015, granted, now 9,653,611, issued on May 16, 2017.
Claims priority of application No. 2014-045406 (JP), filed on Mar. 7, 2014.
Prior Publication US 2021/0398988 A1, Dec. 23, 2021
Int. Cl. H10B 69/00 (2023.01); H01L 29/786 (2006.01); H01L 27/06 (2006.01); G11C 7/16 (2006.01); G11C 8/14 (2006.01); G11C 11/403 (2006.01); G11C 11/408 (2006.01); H10B 41/20 (2023.01); H10B 41/70 (2023.01); G11C 11/24 (2006.01); H01L 29/24 (2006.01)
CPC H10B 69/00 (2023.02) [G11C 7/16 (2013.01); G11C 8/14 (2013.01); G11C 11/24 (2013.01); G11C 11/403 (2013.01); G11C 11/4085 (2013.01); H01L 27/0688 (2013.01); H01L 29/24 (2013.01); H01L 29/7869 (2013.01); H10B 41/20 (2023.02); H10B 41/70 (2023.02)] 11 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a memory cell including first to cth sub memory cells (c is a natural number greater than or equal to 2),
wherein a jth sub memory cell includes a first transistor, a capacitor, and a second transistor (j is a natural number of 1 to c),
wherein a first semiconductor layer in the first transistor and a second semiconductor layer in the second transistor include an oxide semiconductor,
wherein one of terminals of the capacitor is electrically connected to a gate of the second transistor through a plug,
wherein the one of the terminals of the capacitor is electrically connected to one of a source electrode and a drain electrode of the first transistor through a plug,
wherein, when j≥2, the jth sub memory cell is arranged over a j-lth sub memory cell,
wherein a bit line is electrically connected to an other of the source electrode and the drain electrode of the first transistor of the jth sub memory cell, and
wherein the bit line is electrically connected to one of a source electrode and a drain electrode of the first transistor of the j-lth sub memory cell.