US 11,751,404 B2
FinFET transistor based resistive random access memory
Abhishek Sharma, Hillsboro, OR (US); Gregory Chen, Portland, OR (US); Phil Knag, Hillsboro, OR (US); Ram Krishnamurthy, Portland, OR (US); Raghavan Kumar, Hillsboro, OR (US); Sasikanth Manipatruni, Portland, OR (US); Amrita Mathuriya, Portland, OR (US); Huseyin Sumbul, Portland, OR (US); and Ian A. Young, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 25, 2018, as Appl. No. 16/141,025.
Prior Publication US 2020/0098826 A1, Mar. 26, 2020
Int. Cl. H01L 27/24 (2006.01); H10B 63/00 (2023.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H10N 70/00 (2023.01)
CPC H10B 63/30 (2023.02) [H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H10N 70/021 (2023.02); H10N 70/826 (2023.02); H10N 70/882 (2023.02); H10N 70/8833 (2023.02)] 25 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a FinFET transistor including a fin structure on a substrate, wherein the fin structure includes a channel region, a source region adjacent to the channel region, and a drain region adjacent to the channel region, an epitaxial layer around the source region or the drain region; and
a resistive random access memory (RRAM) storage stack wrapped around a surface of the epitaxial layer, the RRAM storage stack including:
a resistive switching material layer in contact and wrapped around the surface of the epitaxial layer; and
a contact electrode in contact and wrapped around a surface of the resistive switching material layer, wherein the epitaxial layer, the resistive switching material layer, and the contact electrode form a RRAM storage cell.