US 11,751,403 B1
Common mode compensation for 2T1C non-linear polar material based memory bit-cell
Rajeev Kumar Dokania, Beaverton, OR (US); Noriyuki Sato, Hillsboro, OR (US); Tanay Gosavi, Portland, OR (US); Amrita Mathuriya, Portland, OR (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Nov. 1, 2021, as Appl. No. 17/516,526.
Application 17/516,526 is a continuation of application No. 17/516,293, filed on Nov. 1, 2021.
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/04 (2006.01); H10B 53/30 (2023.01); H10B 53/40 (2023.01); G11C 11/404 (2006.01)
CPC H10B 53/30 (2023.02) [G11C 11/404 (2013.01); H10B 53/40 (2023.02)] 20 Claims
OG exemplary drawing
 
10. An apparatus comprising:
an array of bit-cells organized in rows and columns, wherein an individual bit-cell includes:
a storage node;
a first capacitor comprising non-linear polar material, the first capacitor having a first terminal coupled to the storage node and a second terminal;
a first transistor coupled to the storage node and a bit-line, wherein the first transistor is controllable by a word-line;
a second transistor coupled to the second terminal of the first capacitor, wherein the second transistor is coupled to a first plate-line, and wherein the second transistor is controllable by the word-line;
a second capacitor coupled to the storage node and a second plate-line, wherein the second capacitor comprises a linear dielectric; and
a driver circuitry to drive a first voltage on the first plate-line and to drive a second voltage on the second plate-line, wherein the first voltage is an inverse of the second voltage.