CPC H10B 53/30 (2023.02) [G11C 11/404 (2013.01); H10B 53/40 (2023.02)] | 20 Claims |
10. An apparatus comprising:
an array of bit-cells organized in rows and columns, wherein an individual bit-cell includes:
a storage node;
a first capacitor comprising non-linear polar material, the first capacitor having a first terminal coupled to the storage node and a second terminal;
a first transistor coupled to the storage node and a bit-line, wherein the first transistor is controllable by a word-line;
a second transistor coupled to the second terminal of the first capacitor, wherein the second transistor is coupled to a first plate-line, and wherein the second transistor is controllable by the word-line;
a second capacitor coupled to the storage node and a second plate-line, wherein the second capacitor comprises a linear dielectric; and
a driver circuitry to drive a first voltage on the first plate-line and to drive a second voltage on the second plate-line, wherein the first voltage is an inverse of the second voltage.
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