US 11,751,402 B2
Ferroelectric capacitors with backend transistors
Abhishek A. Sharma, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Appl. No. 16/636,199
Filed by INTEL CORPORATION, Santa Clara, CA (US)
PCT Filed Sep. 29, 2017, PCT No. PCT/US2017/054603
§ 371(c)(1), (2) Date Feb. 3, 2020,
PCT Pub. No. WO2019/066967, PCT Pub. Date Apr. 4, 2019.
Prior Publication US 2020/0373312 A1, Nov. 26, 2020
Int. Cl. H10B 53/30 (2023.01); G11C 7/18 (2006.01); G11C 8/14 (2006.01); G11C 11/22 (2006.01); H01L 29/423 (2006.01)
CPC H10B 53/30 (2023.02) [G11C 7/18 (2013.01); G11C 8/14 (2013.01); G11C 11/221 (2013.01); G11C 11/223 (2013.01); H01L 29/42384 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a backend thin-film transistor (TFT) having a gate electrode, source and drain regions, a semiconductor region between and physically connecting the source and drain regions along a direction from the source region to the drain region, and a gate dielectric between the gate electrode and the semiconductor region, wherein the gate electrode is a bottom gate electrode, the bottom gate electrode extending laterally beyond outermost sides of the source and drain regions along the direction from the source region to the drain region, and the bottom gate electrode extending laterally beyond outermost sides of the gate dielectric along the direction from the source region to the drain region; and
a ferroelectric capacitor electrically connected to the backend TFT and having a first terminal electrically connected to one of the source and drain regions, a second terminal, and a ferroelectric dielectric between the first and second terminals.