US 11,751,396 B2
Microelectronic devices including varying tier pitch, and related electronic systems
Yifen Liu, Meridian, ID (US); Tecla Ghilardi, Trescore Balneario (IT); George Matamis, Eagle, ID (US); Justin D. Shepherdson, Meridian, ID (US); Nancy M. Lomeli, Boise, ID (US); Chet E. Carter, Boise, ID (US); and Erik R. Byers, Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 20, 2022, as Appl. No. 17/648,528.
Application 17/648,528 is a continuation of application No. 16/904,317, filed on Jun. 17, 2020, granted, now 11,264,404.
Prior Publication US 2022/0139958 A1, May 5, 2022
Int. Cl. H10B 43/27 (2023.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 23/522 (2006.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/35 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/53257 (2013.01); H01L 23/53271 (2013.01); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/35 (2023.02)] 17 Claims
OG exemplary drawing
 
1. A microelectronic device, comprising:
a stack structure comprising tiers each comprising a level of conductive material and a level of insulative material vertically neighboring the level of conductive material, a vertical thickness of a lowermost one of the tiers larger than a vertical thickness of an uppermost one of the tiers, a vertical thickness of the insulative material of the lowermost one of the tiers greater than a vertical thickness of the insulative material of the uppermost one of the tiers; and
strings of memory cells vertically extending through the stack structure.