US 11,751,393 B2
Memory arrays and methods used in forming a memory array comprising strings of memory cells
Manzar Siddik, Boise, ID (US); Chris M. Carlson, Nampa, ID (US); Terry H. Kim, Boise, ID (US); Kunal Shrotri, Boise, ID (US); and Srinath Venkatesan, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 12, 2021, as Appl. No. 17/524,987.
Application 17/524,987 is a division of application No. 16/705,388, filed on Dec. 6, 2019, granted, now 11,205,660.
Prior Publication US 2022/0077186 A1, Mar. 10, 2022
Int. Cl. H01L 27/11582 (2017.01); H10B 43/27 (2023.01); H01L 21/3215 (2006.01); H01L 21/3115 (2006.01); H10B 41/27 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 21/3115 (2013.01); H01L 21/3215 (2013.01); H10B 41/27 (2023.02)] 26 Claims
OG exemplary drawing
 
1. A memory array comprising strings of memory cells, comprising:
a vertical stack comprising alternating insulative tiers and conductive tiers;
strings of memory cells in the stack comprising channel-material strings comprising channel material and storage-material strings comprising storage material, the storage-material strings extending through the insulative tiers and the conductive tiers; and
at least some of the storage material of the storage-material strings in individual of the insulative tiers being intrinsically less charge-transmissive than is the storage material in the storage-material strings in individual of the conductive tiers.