US 11,751,392 B2
Fabrication method for a 3-dimensional NOR memory array
Eli Harari, Saratoga, CA (US); Scott Brad Herner, Portland, OR (US); and Wu-Yi Chien, San Jose, CA (US)
Assigned to SunRise Memory Corporation, San Jose, CA (US)
Filed by Sunrise Memory Corporation, San Jose, CA (US)
Filed on Oct. 14, 2021, as Appl. No. 17/501,917.
Application 17/501,917 is a continuation of application No. 16/914,089, filed on Jun. 26, 2020, granted, now 11,177,281.
Application 16/914,089 is a continuation of application No. 16/510,610, filed on Jul. 12, 2019, granted, now 10,741,581, issued on Aug. 11, 2020.
Claims priority of provisional application 62/697,085, filed on Jul. 12, 2018.
Prior Publication US 2022/0037356 A1, Feb. 3, 2022
Int. Cl. H01L 21/00 (2006.01); H01L 27/00 (2006.01); H01L 29/00 (2006.01); H10B 43/27 (2023.01); H01L 21/306 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 29/08 (2006.01); H01L 21/027 (2006.01); H01L 21/3105 (2006.01)
CPC H10B 43/27 (2023.02) [H01L 21/0273 (2013.01); H01L 21/02164 (2013.01); H01L 21/02532 (2013.01); H01L 21/02579 (2013.01); H01L 21/02595 (2013.01); H01L 21/02636 (2013.01); H01L 21/30604 (2013.01); H01L 21/31053 (2013.01); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 29/0847 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A process for forming a memory structure over a planar surface of a semiconductor substrate, comprising:
forming above the semiconductor substrate a plurality of active stacks placed substantially at predetermined positions along a first direction that is substantially parallel to the planar surface, separated one from another by a first electrically insulative material, each active stack extending lengthwise along a second direction that is (i) substantially parallel to the planar surface and (ii) substantially orthogonal the first direction, wherein (i) each active stack comprises a plurality of active strips, provided along at predetermined positions along a third direction that is substantially orthogonal to the planar surface, each active strip being separated one from another by a first isolation layer; and (ii) each active strip comprises (a) first and second semiconductor layers of a first conductivity type, and (b) a second isolation layer separating the first and the second semiconductor layers;
patterning and etching the first electrically insulative material to provide a plurality of openings at predetermined positions along the first direction, the openings each extending along the third direction, exposing sidewalls of the active stacks on opposite sides of the opening;
etching the second isolation layer of each active strip through the openings, thereby creating recesses between the first and the second semiconductor layers at opposite sides of the second isolation layer;
conformally depositing a third semiconductor layer, the third semiconductor layer being of a second conductivity opposite the first conductivity, such that the third semiconductor layer lines the sidewalls of the opening and one or more walls of the recesses of each active strip;
anisotropically etching the third semiconductor layer to remove the third semiconductor layer from the sidewalls of the openings;
conformally depositing a charge-trapping material on the sidewalls of the opening, such that the third semiconductor layer in the recesses are in contact with the charge-trapping layer; and
filling the openings with a conductive material.