CPC H10B 43/27 (2023.02) [H01L 29/40117 (2019.08); H01L 29/513 (2013.01); H01L 29/517 (2013.01); H01L 29/518 (2013.01)] | 27 Claims |
1. A process, comprising:
providing over a planar surface of a semiconductor substrate first and second multi-layer structures that are separated by a trench with a predetermined width, as measured along a first direction that is substantially parallel the planar surface, each multi-layer structure comprising a plurality of multi-layer active strips each extending lengthwise along a second direction that is substantially orthogonal to the first direction and which are stacked one on top of another along a third direction that is substantially normal to the planar surface, wherein adjacent ones of the multi-layer active strips are electrically isolated from each other by a layer of an isolation material, and wherein each active multi-layer strip comprises first and second conductive layers separated by a dielectric material;
recessing the sidewalls of the trench at the multi-layer strips along the first direction, thereby creating recesses between adjacent layers of isolation material; providing in the recesses a predetermined material; filling the trench with a first filler material; forming first and second shafts at a predetermined distance along the second direction by removing in each shaft a portion of each multi-layer strip from each of the first and second multi-layer structures and a portion of the isolation material from the trench;
filling the first and second shafts with a second filler material;
removing the first filler material from the trench between the first and second shafts;
providing a data storage layer conformally on the sidewalls of the trench and filling the remainder of the trench with a conductive material.
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