US 11,751,388 B2
3-dimensional nor strings with segmented shared source regions
Eli Harari, Saratoga, CA (US); and Raul Adrian Cernea, Santa Clara, CA (US)
Assigned to SunRise Memory Corporation, San Jose, CA (US)
Filed by SunRise Memory Corporation, San Jose, CA (US)
Filed on Apr. 14, 2022, as Appl. No. 17/721,247.
Application 16/792,808 is a division of application No. 16/006,612, filed on Jun. 12, 2018, granted, now 10,608,008, issued on Mar. 31, 2020.
Application 17/721,247 is a continuation of application No. 17/170,664, filed on Feb. 8, 2021, granted, now 11,335,693.
Application 17/170,664 is a continuation of application No. 16/792,808, filed on Feb. 17, 2020, granted, now 10,950,616, issued on Mar. 16, 2021.
Claims priority of provisional application 62/522,665, filed on Jun. 20, 2017.
Prior Publication US 2022/0238545 A1, Jul. 28, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/18 (2006.01); H10B 43/20 (2023.01); H03K 19/20 (2006.01); H03K 19/1776 (2020.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); H01L 29/786 (2006.01)
CPC H10B 43/20 (2023.02) [G11C 7/18 (2013.01); G11C 16/0466 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01); H03K 19/1776 (2013.01); H03K 19/20 (2013.01); H01L 29/78696 (2013.01)] 12 Claims
OG exemplary drawing
 
1. An array of NOR memory strings, formed above a planar surface of a semiconductor substrate, the memory array comprising:
a channel layer extending lengthwise along a first direction that substantially parallels the planar surface;
a source layer and a drain layer each being in contact with the channel layer but separated from each other, the source layer and the drain layer each extending lengthwise along the first direction, wherein (i) the source layer comprises a first segment and a second segment that are electrically isolated from each other, (ii) a first portion of the channel layer, the first segment of the source layer and the drain layer form storage transistors of a first one of the NOR memory strings, and a second portion of the channel layer, the second segment of the source layer and the drain layer form storage transistors of a second one of the NOR memory strings; and (iii) as to storage transistors in each NOR memory string, the drain layer provides a common bit line, and the corresponding segment of the source layer provides a common source line;
a layer of storage material provided in a trench that runs lengthwise along the first direction through the drain layer, the source layer and the channel layer; and
a plurality of conductors to serve as local word lines.