US 11,751,347 B2
Electronic apparatus
Akitoshi Suzuki, Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Apr. 21, 2022, as Appl. No. 17/660,075.
Application 17/660,075 is a continuation of application No. 17/120,982, filed on Dec. 14, 2020, granted, now 11,357,123.
Application 17/120,982 is a continuation of application No. 16/662,558, filed on Oct. 24, 2019, granted, now 10,905,021, issued on Jan. 26, 2021.
Application 16/662,558 is a continuation of application No. 15/824,125, filed on Nov. 28, 2017, granted, now 10,512,182, issued on Dec. 17, 2019.
Claims priority of application No. 2017-031040 (JP), filed on Feb. 22, 2017; and application No. 2017-149384 (JP), filed on Aug. 1, 2017.
Prior Publication US 2022/0248554 A1, Aug. 4, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H05K 5/02 (2006.01); H05K 7/20 (2006.01); G06F 3/06 (2006.01); G06F 1/18 (2006.01); H05K 1/02 (2006.01); H05K 1/14 (2006.01)
CPC H05K 5/0269 (2013.01) [G06F 1/182 (2013.01); G06F 3/0688 (2013.01); H05K 7/20472 (2013.01); H05K 1/0275 (2013.01); H05K 1/144 (2013.01); H05K 7/20454 (2013.01); H05K 2201/042 (2013.01); H05K 2201/10159 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A solid state drive comprising:
a first printed circuit board having a first main surface and a second main surface, the second main surface opposing the first main surface;
a flash memory;
a first encryption device mounted on the first main surface, the first encryption device being configured to encrypt data to be stored in the flash memory; and
a housing including a wall and a first plate, the housing accommodating the first printed circuit board, the flash memory, and the first encryption device,
the wall including a first region and a second region, the first region including an opening, the second region including no opening,
the first plate having a first surface, the first surface facing the first main surface of the first printed circuit board,
wherein
the second region of the wall is bounded by a first position and a second position,
the first position being a position where the wall is intersected by an imaginary extension of the first main surface of the first printed circuit board,
the second position being a position where the wall is intersected by an imaginary extension of the first surface of the first plate.