CPC H04W 56/0035 (2013.01) [H04L 5/0048 (2013.01); H04W 56/004 (2013.01); H04W 72/23 (2023.01)] | 26 Claims |
1. An apparatus for wireless communication, comprising:
a transceiver;
a memory configured to store instructions; and
one or more processors coupled with the memory and the transceiver, wherein the one or more processors are configured to:
receive a demodulation reference signal (DMRS) that can be used to perform channel estimation for a downlink control channel, wherein a sequence of the DMRS indicates a time offset from the downlink control channel to a downlink data channel;
buffer, based on receiving the DMRS and until a time at which the time offset is determined from the sequence of the DMRS, samples of the downlink data channel associated with the downlink control channel;
flush buffered samples of the downlink data channel where the time offset from the downlink control channel is after the time at which the time offset is determined from the sequence of the DMRS; and
process at least a portion of the buffered samples of the downlink data channel where the time offset from the downlink control channel is before the time at which the time offset is determined from the sequence of the DMRS.
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