CPC H04W 4/70 (2018.02) [G06F 3/061 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); H04W 72/0453 (2013.01); H04W 72/12 (2013.01); H04W 72/1215 (2013.01); H04W 72/23 (2023.01); H04W 74/02 (2013.01); H04W 74/04 (2013.01); H04W 74/08 (2013.01); H04W 76/14 (2018.02); H04W 88/06 (2013.01); H04W 92/18 (2013.01)] | 20 Claims |
1. An apparatus, comprising:
a host processor; and
a main memory capable of being wirelessly coupled to the host processor via a communication link utilizing fifth generation (5G) technology, the main memory configured to communicate with the host processor on a sidelink within a licensed frequency band on time and frequency resources schedulable via downlink control signaling from a base station.
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