US 11,750,951 B2
Solid-state imaging element, imaging apparatus, and control method of solid-state imaging element with improved reading speed of pixel signals
Shinichirou Etou, Kanagawa (JP); Yosuke Ueno, Kanagawa (JP); Yasufumi Hino, Kanagawa (JP); and Kazutoshi Tomita, Kanagawa (JP)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Filed by Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Filed on May 3, 2022, as Appl. No. 17/735,347.
Application 17/735,347 is a continuation of application No. 16/761,224, granted, now 11,368,644, previously published as PCT/JP2018/035166, filed on Sep. 21, 2018.
Claims priority of application No. 2017-216980 (JP), filed on Nov. 10, 2017; and application No. 2018-025772 (JP), filed on Feb. 16, 2018.
Prior Publication US 2022/0264051 A1, Aug. 18, 2022
Int. Cl. H04N 25/772 (2023.01); H01L 27/146 (2006.01); H04N 25/71 (2023.01); H03M 1/46 (2006.01); H03M 1/12 (2006.01)
CPC H04N 25/772 (2023.01) [H01L 27/14612 (2013.01); H01L 27/14636 (2013.01); H01L 27/14643 (2013.01); H04N 25/745 (2023.01)] 17 Claims
OG exemplary drawing
 
1. A device comprising:
a plurality of pixels arranged in rows and columns;
a plurality of column lines, each of the plurality of column lines being coupled to a respective column of pixels of the plurality of pixels; and
circuitry comprising a plurality of analog-to-digital converters, at least one of the plurality of analog-to-digital converters being coupled to at least two column lines of the plurality of column lines,
wherein the at least one of the plurality of analog-to-digital converters comprises a comparator configured to compare a reference signal with a pixel signal provided to the comparator through one of the at least two column lines, and
wherein the comparator comprises:
a first transistor configured to receive, at a gate terminal thereof, a first pixel signal provided through a first column line of the at least two column lines;
a second transistor configured to receive, at a gate terminal thereof, a second pixel signal provided through a second column line of the at least two column lines; and
a third transistor configured to receive, at a gate terminal thereof, the reference signal,
wherein the at least one of the plurality of analog-to-digital converters comprises successive approximation register logic circuitry coupled to the comparator.