CPC H04N 25/772 (2023.01) [H01L 27/14612 (2013.01); H01L 27/14636 (2013.01); H01L 27/14643 (2013.01); H04N 25/745 (2023.01)] | 17 Claims |
1. A device comprising:
a plurality of pixels arranged in rows and columns;
a plurality of column lines, each of the plurality of column lines being coupled to a respective column of pixels of the plurality of pixels; and
circuitry comprising a plurality of analog-to-digital converters, at least one of the plurality of analog-to-digital converters being coupled to at least two column lines of the plurality of column lines,
wherein the at least one of the plurality of analog-to-digital converters comprises a comparator configured to compare a reference signal with a pixel signal provided to the comparator through one of the at least two column lines, and
wherein the comparator comprises:
a first transistor configured to receive, at a gate terminal thereof, a first pixel signal provided through a first column line of the at least two column lines;
a second transistor configured to receive, at a gate terminal thereof, a second pixel signal provided through a second column line of the at least two column lines; and
a third transistor configured to receive, at a gate terminal thereof, the reference signal,
wherein the at least one of the plurality of analog-to-digital converters comprises successive approximation register logic circuitry coupled to the comparator.
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