CPC H04N 19/66 (2014.11) [H04N 19/122 (2014.11); H04N 19/176 (2014.11); H04N 19/103 (2014.11); H04N 19/96 (2014.11)] | 3 Claims |
1. An encoder, comprising:
circuitry; and
memory connected to the circuitry,
wherein the circuitry, in operation,
determines a mode to be applied to a block from a plurality of merge modes based on a width of the block and a height of the block,
when the mode determined is a first mode, stores in a bitstream an index indicating a distance and an angle that define two partitions in the block, and encodes the block using the first mode,
disables the first mode and storing of the index in the bitstream when (i) the width is 64 pixels and the height is 8 pixels or (ii) the height is 64 pixels and the width is 8 pixels, and
applies the first mode to the block when (i) a ratio of the width to the height is smaller than 8 and (ii) a ratio of the height to the width is smaller than 8,
wherein the plurality of merge modes include a combined inter merge/intra prediction (CIIP) mode.
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