CPC H04N 19/30 (2014.11) [H04L 69/324 (2013.01); H04N 19/119 (2014.11); H04N 19/166 (2014.11); H04N 19/174 (2014.11); H04N 19/187 (2014.11); H04N 19/33 (2014.11); H04N 19/423 (2014.11); H04N 19/44 (2014.11); H04N 19/50 (2014.11); H04N 19/593 (2014.11); H04N 19/65 (2014.11); H04N 19/66 (2014.11); H04N 19/70 (2014.11); H04N 19/85 (2014.11); H04N 19/89 (2014.11); H04N 19/91 (2014.11)] | 20 Claims |
1. A decoder comprising a processor configured to decode a multi-layered video data stream that includes encoded video content represented in a plurality of layers, the multi-layered video data stream including a sequence of network abstraction layer (NAL) units, which are divided into a sequence of access units,
wherein each access unit includes a plurality of decoding units, with each decoding unit of the plurality of decoding units having at least one NAL unit corresponding to one layer of the plurality of layers, and
wherein the multi-layered video data stream includes:
first timing control information in the multi-layered video data stream signaling a first decoder buffer retrieval time for an access unit from the sequence of access units, and
second timing control information in the multi-layered video data stream, separate from the first timing control information, the second timing control information signaling a second decoder buffer retrieval time for each decoding unit of a particular access unit according to a sequential order of the respective decoding unit in the multi-layered video data stream.
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