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1. An FPGA device for implementing expansion of a transmission bandwidth of a network-on-chip, wherein the FPGA device comprises an FPGA bare die, the FPGA bare die comprising a plurality of logical resource modules, the FPGA die further comprising a predefined functional module integrated inside, the predefined functional module comprising N built-in hardcore IP nodes, adjacent hardcore IP nodes being connected through routing channels, input and output signals of the predefined functional module being connected to the hardcore IP nodes; FPGA bare die further comprises M soft-core IP nodes configured and formed through the logical resource modules therein; the hardcore IP nodes and the softcore IP nodes in the FPGA bare die are connected through the routing channels to form an NOC network structure, the nodes comprising N hardcore nodes and M soft-core nodes, each of the nodes comprising a functional IP, a network interface and a router respectively, the functional IP being connected to the router through the network interface, the routers in every two adjacent nodes being connected through the routing channels; and the predefined functional module intercommunicates with external signals through the N built-in hardcore IP nodes and the M soft-core IP nodes formed by expansion.
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