US 11,750,403 B2
Robust state synchronization for stateful hash-based signatures
Manoj Sastry, Portland, OR (US); Rafael Misoczki, Hillsboro, OR (US); Jordan Loney, Hillsboro, OR (US); and David M. Wheeler, Chandler, AZ (US)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jul. 29, 2022, as Appl. No. 17/816,148.
Application 17/816,148 is a continuation of application No. 16/830,844, filed on Mar. 26, 2020, granted, now 11,438,172.
Prior Publication US 2022/0368537 A1, Nov. 17, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 21/72 (2013.01); H04L 9/32 (2006.01)
CPC H04L 9/3247 (2013.01) [G06F 21/72 (2013.01); H04L 9/3236 (2013.01)] 15 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
hardware processing circuitry to:
select, from the plurality of hardware security modules, a set of hardware security modules to be assigned to a digital signature process, the set of hardware security modules comprising at least a first hardware security module and a second hardware module;
assign a set of unique state synchronization counter sequences to the respective set of hardware security modules, the set of state synchronization counter sequences comprising at least a first state synchronization counter sequence and a second state synchronization counter sequence;
select a set of hardware security modules to be assigned to a digital signature process, the set of hardware security modules comprising at least a first hardware security module and a second hardware module and a third hardware security module; and
assign a set of unique state synchronization counter sequences to the respective set of hardware security modules, the set of state synchronization counter sequences comprising at least a first state synchronization counter sequence and a second state synchronization counter sequence and a third synchronization counter sequence, wherein:
the first set of state synchronization counter sequences comprises a first plurality of counters selected from only integers which are evenly divisible by 3 and is assigned to the first hardware security module;
the second set of state synchronization counter sequences comprises a second plurality of counters selected from only integers which, when divided by 3, result in a remainder of 1, and is assigned to the second hardware security module; and
the third set of state synchronization counter sequences comprises a third plurality of counters selected from only integers which, when divided by 3, result in a remainder of 2, and is assigned to the third hardware security module.