CPC H04L 9/002 (2013.01) [G06F 7/582 (2013.01); G06F 7/588 (2013.01); H04L 9/003 (2013.01); H04L 9/004 (2013.01); H04L 2209/08 (2013.01); H04L 2209/12 (2013.01)] | 20 Claims |
1. A system comprising:
a processor configured to be driven by a randomized clock signal; and
a variable clock configured to generate the randomized clock signal from a received input clock signal, the variable clock comprising:
a variable delay generator comprising a phase interpolator configured to produce a variable delay amount;
a fixed delay generator configured to generate a fixed delay amount;
circuitry configured to combine the fixed delay amount and the variable delay amount to create a combined delay amount; and
an output configured to generate the randomized clock signal responsive to the combined delay amount elapsing since receiving the input clock signal.
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