CPC H04L 1/02 (2013.01) [H03K 19/0175 (2013.01); H04L 25/0272 (2013.01); H04L 25/062 (2013.01); H04L 2025/03363 (2013.01)] | 19 Claims |
1. An apparatus comprising:
circuitry configured to:
receive a first plurality of signals via an interface at a first point in time;
generate a first sequence of bits based on the first plurality of signals and an average voltage level of the first plurality of signals; and
receive a second plurality of signals via the interface at a second point in time;
generate a second sequence of bits, with at least one value different from the first sequence of bits, based on the second plurality of signals and an average voltage level of the second plurality of signals;
wherein the first sequence of bits and the second sequence of bits represent a same data word.
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