US 11,750,290 B2
Receiver synchronization for higher speed passive optical networks
Rainer Strobel, Munich (DE); and Gert Schedelbeck, Munich (DE)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 10, 2020, as Appl. No. 17/117,206.
Claims priority of provisional application 62/947,600, filed on Dec. 13, 2019.
Prior Publication US 2021/0184771 A1, Jun. 17, 2021
Int. Cl. H04B 10/27 (2013.01); H04L 7/00 (2006.01); H04L 1/00 (2006.01)
CPC H04B 10/27 (2013.01) [H04L 1/004 (2013.01); H04L 7/0075 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit for a passive optical network (PON) comprising:
one or more processors configured to:
operate in a hunt state, wherein the one or more processors is configured to detect frame boundaries associated with an incoming data signal based on detecting a predefined synchronization (psync) pattern associated with a set of hunt frames comprising one or more consecutive frames associated with the incoming data signal;
transition to a pre-sync state if the predefined psync pattern is detected correctly for at least one frame of the set of hunt frames; and
operate in the pre-sync state, wherein the one or more processors is configured to perform forward error correction (FEC) decoding on a payload data portion of a set of pre-sync frames comprising one or more subsequent consecutive frames associated with the incoming data signal and detect a loss of synchronization in the pre-sync state based on the FEC decoding on the payload data portion.