CPC H04B 10/25133 (2013.01) [H03M 1/00 (2013.01); H04B 10/2569 (2013.01)] | 20 Claims |
1. An optical Digital Signal Processor (DSP) circuit comprising:
a digital core configured to implement digital signal processing functionality and configured to operate at a plurality of baud rates including a full baud rate and a half-baud rate; and
an analog interface comprising a Digital-to-Analog Converter (DAC) section and an Analog-to-Digital Converter (ADC) section, wherein the analog interface is connected to the digital core and is configured to operate at the full baud rate when the digital core is configured to operate at any of the plurality of baud rates, wherein the analog interface includes a plurality of dividers and multiplexers to half a clock from the analog interface to the digital core when the digital core operates at the half-baud rate.
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