US 11,750,226 B2
Error correction code system with augmented detection features
Eric Masson, Fremont, CA (US); and Nagaraju Balasubramanya, Fremont, CA (US)
Assigned to NVIDIA CORPORATION, Santa Clara, CA (US)
Filed by NVIDIA CORPORATION, Santa Clara, CA (US)
Filed on Jun. 9, 2021, as Appl. No. 17/343,136.
Prior Publication US 2022/0399905 A1, Dec. 15, 2022
Int. Cl. H03M 13/29 (2006.01); G06F 11/10 (2006.01)
CPC H03M 13/2906 (2013.01) [G06F 11/1076 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A computer-implemented method for detecting errors in a memory, the method comprising:
retrieving first data associated with a first store operation directed towards a memory address that was generated according to a memory access pattern;
generating a first error correction code (ECC) code based on the first data and at least one of address information or sequencing information associated with the first store operation;
storing the first data and the first ECC code at the memory address;
in response to a load operation, reading the first data and the first ECC code from the memory address; and
regenerating the at least one of the address information or the sequencing information associated with the first store operation based on the memory access pattern.