US 11,750,222 B1
Throughput efficient Reed-Solomon forward error correction decoding
Venugopal Santhanam, Karnataka (IN); and Aman Mishra, Karnataka (IN)
Assigned to SYNOPSYS, INC., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Jun. 29, 2022, as Appl. No. 17/809,715.
Int. Cl. H03M 13/00 (2006.01); H03M 13/15 (2006.01)
CPC H03M 13/1515 (2013.01) [H03M 13/1575 (2013.01); H03M 13/6516 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A Reed-Solomon decoder circuit comprising:
a syndrome calculator circuit configured to compute syndrome values for a first codeword and a second codeword sequentially supplied to the syndrome calculator circuit, where last symbols of the first codeword overlap with first symbols of the second codeword during an overlap clock cycle between:
a first plurality of non-overlap clock cycles during which the first codeword is supplied to the syndrome calculator circuit; and
a second plurality of non-overlap clock cycles during which the second codeword is supplied to the syndrome calculator circuit;
an error locator and error evaluator polynomial calculator circuit configured to compute error locator polynomials and error evaluator polynomials based on the syndrome values;
an error location and error value calculator circuit configured to compute error locations based on the error locator polynomials and Forney numerator and denominator values based on the error evaluator polynomials;
an error counter and error evaluator circuit configured to count errors based on the error locations and compute error magnitudes based on the Forney numerator and denominator values; and
an error corrector circuit configured to correct the errors in the first codeword and the second codeword based on the error counts and the error magnitudes.