US 11,750,201 B2
Delay line, a delay locked loop circuit and a semiconductor apparatus using the delay line and the delay locked loop circuit
Yun Tack Han, Icheon-si (KR); and Kyeong Min Kim, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si Gyeonggi-do (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jun. 14, 2021, as Appl. No. 17/347,312.
Application 17/347,312 is a continuation in part of application No. 17/149,479, filed on Jan. 14, 2021.
Application 17/149,479 is a continuation in part of application No. 16/911,888, filed on Jun. 25, 2020, granted, now 11,206,026.
Claims priority of application No. 10-2019-0110563 (KR), filed on Sep. 6, 2019; and application No. 10-2019-0110569 (KR), filed on Sep. 6, 2019.
Prior Publication US 2021/0305989 A1, Sep. 30, 2021
Int. Cl. H03L 7/081 (2006.01); H03K 5/134 (2014.01); H03L 7/089 (2006.01); H03L 7/087 (2006.01)
CPC H03L 7/0816 (2013.01) [H03K 5/134 (2014.07); H03L 7/0895 (2013.01); H03L 7/087 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A delay locked loop circuit comprising:
a frequency detector configured to detect a frequency of a reference clock signal to generate a frequency detection signal;
a delay line configured to delay, based on a delay control voltage, the reference clock signal to generate an internal clock signal and a feedback clock signal;
a phase detector configured to compare phases of the internal clock signal and the feedback clock signal to generate a first detection signal and a second detection signal;
a selection controller configured to provide the first detection signal and the second detection signal respectively as an up-signal and a down-signal when the frequency detection signal is disabled, and to provide the reference clock signal as the up-signal and the down-signal when the frequency detection signal is enabled; and
a charge pump configured to generate the delay control voltage based on the up-signal and the down-signal.