US 11,750,194 B2
Semiconductor device
Masashi Fujita, Tokyo (JP); Yutaka Shionoiri, Kanagawa (JP); Kiyoshi Kato, Kanagawa (JP); and Hidetomo Kobayashi, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Jan. 15, 2021, as Appl. No. 17/150,859.
Application 17/150,859 is a continuation of application No. 16/705,326, filed on Dec. 6, 2019, granted, now 10,897,258.
Application 16/705,326 is a continuation of application No. 15/610,705, filed on Jun. 1, 2017, granted, now 10,505,547, issued on Dec. 10, 2019.
Application 15/610,705 is a continuation of application No. 13/469,143, filed on May 11, 2012, granted, now 9,762,246, issued on Sep. 12, 2017.
Claims priority of application No. 2011-113057 (JP), filed on May 20, 2011.
Prior Publication US 2021/0135674 A1, May 6, 2021
Int. Cl. H03K 19/173 (2006.01); H03K 19/17728 (2020.01); H03K 19/17772 (2020.01); H03K 19/17758 (2020.01)
CPC H03K 19/17728 (2013.01) [H03K 19/1737 (2013.01); H03K 19/17758 (2020.01); H03K 19/17772 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A semiconductor device comprising a circuit, the circuit comprising:
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a first capacitor; and
a second capacitor,
wherein one electrode of the first capacitor is electrically connected to one electrode of the second capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein a gate of the first transistor is electrically connected to a gate of the second transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the third transistor,
wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein the first transistor comprises an oxide semiconductor in a channel formation region,
wherein the second transistor comprises an oxide semiconductor in a channel formation region, and
wherein the third transistor comprises crystalline silicon in a channel formation region.