US 11,750,185 B2
Calibrated linear duty cycle correction
Siva Charan Nimmagadda, Nellore (IN); Xiaobao Wang, Cupertino, CA (US); Vinit Shah, Cupertino, CA (US); Sabarathnam Ekambaram, Secunderabad (IN); and Hari Bilash Dubey, Hyderabad (IN)
Assigned to XILINX, INC., San Jose, CA (US)
Filed by XILINX, INC., San Jose, CA (US)
Filed on Sep. 22, 2021, as Appl. No. 17/482,336.
Prior Publication US 2023/0086781 A1, Mar. 23, 2023
Int. Cl. H03K 5/156 (2006.01); H03K 5/134 (2014.01); H03K 5/135 (2006.01); G11C 7/22 (2006.01)
CPC H03K 5/1565 (2013.01) [G11C 7/222 (2013.01); H03K 5/134 (2014.07); H03K 5/135 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit for correcting an input clock signal, comprising:
a first leg circuit; and
a second leg circuit;
wherein the first leg circuit and the second leg circuit both comprise a charging circuit and a discharging circuit, wherein each charging circuit comprises a first plurality of transistors in series and each discharging circuit comprises a second plurality of transistors in series, wherein the charging circuit is coupled to the discharging circuit in series;
wherein a number of transistors of the first plurality of transistors in the first leg circuit is different from a number of transistors of the first plurality of transistors in the second leg circuit.