US 11,750,181 B2
Digital phase interpolator, clock signal generator, and volatile memory device including the clock signal generator
Junsub Yoon, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jan. 13, 2022, as Appl. No. 17/575,020.
Claims priority of application No. 10-2021-0072399 (KR), filed on Jun. 3, 2021.
Prior Publication US 2022/0393673 A1, Dec. 8, 2022
Int. Cl. G11C 11/4093 (2006.01); G11C 11/4076 (2006.01); H03K 5/133 (2014.01); H03K 5/00 (2006.01)
CPC H03K 5/133 (2013.01) [G11C 11/4076 (2013.01); G11C 11/4093 (2013.01); H03K 2005/00052 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A clock signal generator configured to receive an external clock signal and to generate an internal clock signal, the clock signal generator comprising:
an internal signal generator configured to generate a first internal signal and a second internal signal, based on the external clock signal, the first internal signal having a predetermined phase difference relative to the second internal signal;
a first phase interpolator configured to interpolate the first internal signal with the second internal signal in response to a first control signal, and to generate a first interpolation signal that is delayed by 2N times a preset delay step with respect to the first internal signal, wherein N is an integer greater than or equal to 0;
a second phase interpolator configured to interpolate the first internal signal with the second internal signal in response to a second control signal, and to generate a second interpolation signal that is delayed by (2N+1) times the preset delay step with respect to the first internal signal; and
a selector configured to select any one of the first interpolation signal and the second interpolation signal in response to a selection signal, and to output the selected interpolation signal as the internal clock signal.