US 11,750,180 B2
High frequency AC coupled self-biased divider
James Strom, Rochester, MN (US); Grant P. Kesselring, Rochester, MN (US); Andrew D. Davies, Rochester, MN (US); and Ann Chen Wu, Hopewell Junction, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Sep. 8, 2021, as Appl. No. 17/469,402.
Prior Publication US 2023/0073824 A1, Mar. 9, 2023
Int. Cl. H03K 5/01 (2006.01); G06F 1/08 (2006.01)
CPC H03K 5/01 (2013.01) [G06F 1/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit, comprising:
a clock generation circuit configured to generate a differential clocking signal;
a pair of capacitors configured to receive the differential clocking signal; and
a self-biased divider comprising inputs coupled to the pair of capacitors to receive the differential clocking signal, wherein the self-biased divider is configured to output a quadrature clocking signal where at least two clocking signals in the quadrature clocking signal are fed back to perform DC biasing on the differential clocking signal.