CPC H03K 5/01 (2013.01) [G06F 1/08 (2013.01)] | 20 Claims |
1. A circuit, comprising:
a clock generation circuit configured to generate a differential clocking signal;
a pair of capacitors configured to receive the differential clocking signal; and
a self-biased divider comprising inputs coupled to the pair of capacitors to receive the differential clocking signal, wherein the self-biased divider is configured to output a quadrature clocking signal where at least two clocking signals in the quadrature clocking signal are fed back to perform DC biasing on the differential clocking signal.
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