US 11,750,178 B2
Flip-flop with input and output select and output masking that enables low power scan for retention
Thomas Saroshan David, Lakeway, TX (US)
Assigned to Silicon Laboratories Inc., Austin, TX (US)
Filed by Silicon Laboratories Inc., Austin, TX (US)
Filed on Nov. 2, 2021, as Appl. No. 17/517,054.
Prior Publication US 2023/0133269 A1, May 4, 2023
Int. Cl. H03K 3/356 (2006.01); H03K 3/012 (2006.01); H03K 3/037 (2006.01)
CPC H03K 3/356121 (2013.01) [H03K 3/012 (2013.01); H03K 3/0375 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A flip-flop, comprising:
a scan enable input for receiving a scan enable signal;
a clock input for receiving a clock signal;
input select circuitry that is configured to select between a data input and a scan input based on a state of the scan enable signal for providing a selected input on a first node;
latching circuitry comprising a plurality of latches coupled in series between the first node and a preliminary output node that is configured to latch the selected input to the preliminary output node in response to transitions of the clock signal; and
output select circuitry that is configured to provide a state of the preliminary output node to a selected one of a scan output and a data output based on a state of the scan enable signal, and that is configured to mask the preliminary output node from the data output when the scan output is selected, wherein the output select circuitry comprises:
a first pass gate controlled by the scan enable signal having an input coupled to the preliminary output node and having an output, and a first buffer having an input coupled to the output of the first pass gate and having an output providing the data output; and
a second pass gate controlled by the scan enable signal having an input coupled to the preliminary output node and having an output, and a second buffer having an input coupled to the output of the second pass gate and having an output providing the scan output.