US 11,750,163 B2
Deglitching circuit and method in a class-D amplifier
Ru Feng Du, Shenzhen (CN); and Qi Yu Liu, Shenzhen (CN)
Assigned to STMicroelectronics (Shenzhen) R&D Co. Ltd., Shenzhen (CN)
Filed by STMicroelectronics (Shenzhen) R&D Co. Ltd., Shenzhen (CN)
Filed on Mar. 12, 2021, as Appl. No. 17/200,490.
Application 17/200,490 is a continuation of application No. 16/354,760, filed on Mar. 15, 2019, granted, now 10,965,263.
Prior Publication US 2021/0203293 A1, Jul. 1, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H03F 3/217 (2006.01); H03G 1/04 (2006.01); H03K 19/017 (2006.01); H03K 19/20 (2006.01); H03K 19/003 (2006.01); H03G 3/30 (2006.01); H03K 19/096 (2006.01)
CPC H03G 1/04 (2013.01) [H03F 3/2173 (2013.01); H03G 3/3026 (2013.01); H03K 19/00323 (2013.01); H03K 19/01728 (2013.01); H03K 19/096 (2013.01); H03K 19/20 (2013.01); H03F 2200/78 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A class-D amplifier comprising:
a pre-amplifier circuit having an input terminal configured to receive an input signal and an output terminal configured to generate an amplified signal based on the input signal;
an integrator having an input terminal coupled to the output terminal of the pre-amplifier circuit;
a comparator having an input terminal coupled to an output terminal of the integrator;
a deglitching circuit having an input terminal coupled to the output terminal of the comparator; and
a driving circuit having an input terminal coupled to an output terminal of the deglitching circuit, wherein the deglitching circuits comprises:
a first deglitching input terminal configured to receive a first signal,
a deglitching output terminal, and
a logic circuit coupled between the first deglitching input terminal and the deglitching output terminal, the logic circuit comprising a latch having a first logic gate and a second logic gate, an output of the first logic gate being coupled to an input of the second logic gate.