US 11,749,754 B2
Active pattern structure and semiconductor device including the same
Sangmoon Lee, Seoul (KR); Kyungin Choi, Suwon-si (KR); and Seunghun Lee, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd.
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Dec. 14, 2021, as Appl. No. 17/550,712.
Application 17/550,712 is a continuation of application No. 16/887,900, filed on May 29, 2020, granted, now 11,233,151.
Claims priority of application No. 10-2019-0142901 (KR), filed on Nov. 8, 2019.
Prior Publication US 2022/0109065 A1, Apr. 7, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 31/113 (2006.01); H01L 31/119 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/417 (2006.01)
CPC H01L 29/785 (2013.01) [H01L 29/0649 (2013.01); H01L 29/41791 (2013.01); H01L 29/6681 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
an active pattern structure on a substrate, the active pattern structure comprising:
a lower active pattern protruding from an upper surface of the substrate in a vertical direction substantially perpendicular to the upper surface of the substrate;
an upper active pattern directly on the lower active pattern; and
a buffer between the lower active pattern and the upper active pattern, wherein the buffer contacts edge portions of the lower and upper active patterns and comprises aluminum silicon oxide;
an isolation pattern on the substrate, wherein the isolation pattern is on at least a portion of a sidewall of the active pattern structure;
a gate electrode structure on the active pattern structure; and
a source/drain layer on a portion of the active pattern structure adjacent the gate electrode structure.