US 11,749,752 B2
Doping profile for strained source/drain region
Hsueh-Chang Sung, Zhubei (TW); Tsz-Mei Kwok, Hsinchu (TW); Kun-Mu Li, Zhudong Township (TW); Tze-Liang Lee, Hsinchu (TW); and Chii-Horng Li, Zhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Dec. 3, 2020, as Appl. No. 17/110,592.
Application 17/110,592 is a division of application No. 15/589,259, filed on May 8, 2017, granted, now 10,861,971.
Application 15/589,259 is a continuation of application No. 14/134,302, filed on Dec. 19, 2013, granted, now 9,691,898, issued on Jun. 27, 2017.
Prior Publication US 2021/0119048 A1, Apr. 22, 2021
Int. Cl. H01L 29/78 (2006.01); H01L 29/161 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/324 (2006.01); H01L 29/04 (2006.01); H01L 29/08 (2006.01); H01L 29/165 (2006.01)
CPC H01L 29/7848 (2013.01) [H01L 21/02057 (2013.01); H01L 21/02532 (2013.01); H01L 21/324 (2013.01); H01L 29/045 (2013.01); H01L 29/0847 (2013.01); H01L 29/165 (2013.01); H01L 29/6656 (2013.01); H01L 29/66575 (2013.01); H01L 29/66636 (2013.01); H01L 29/7833 (2013.01); H01L 29/66628 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a transistor device, comprising:
forming a gate structure onto a semiconductor substrate;
forming a source/drain recess within the semiconductor substrate adjacent to a side of the gate structure; and
forming a first strain inducing layer within the source/drain recess, wherein the first strain inducing layer comprises a strain inducing component with a strain inducing component concentration profile that continuously decreases from a bottommost surface of the first strain inducing layer to a position above the bottommost surface; and
forming a second strain inducing layer onto the first strain inducing layer, wherein the second strain inducing layer has a bottommost surface that faces the semiconductor substrate and that is below a top of the first strain inducing layer, and wherein the second strain inducing layer comprises a second inducing component concentration profile that increases from the bottommost surface of the second strain inducing layer to a position above the bottommost surface.
 
7. A method of forming a transistor device, comprising:
forming a gate structure onto a substrate;
forming a source/drain recess within the substrate next to the gate structure;
forming a first strain inducing layer onto a horizontally extending surface and sidewalls of the substrate that define the source/drain recess; and
forming a second strain inducing layer within the source/drain recess and onto a horizontally extending surface and along interior sidewalls of the first strain inducing layer that face one another, wherein the first strain inducing layer comprises a first strain inducing component with a first concentration profile that is discontinuous with a second concentration profile of a second strain inducing component within the second strain inducing layer.
 
16. A method of forming a transistor device, comprising:
forming a gate structure onto a substrate;
forming a source/drain recess within the substrate next to the gate structure;
forming a first strain inducing layer in the source/drain recess, wherein the first strain inducing layer has a first concentration profile that decreases as a distance from the substrate increases; and
forming a second strain inducing layer in the source/drain recess, wherein the second strain inducing layer has a second concentration profile that increases as a distance from the first strain inducing layer increases.