CPC H01L 29/42372 (2013.01) [H01L 29/40114 (2019.08); H01L 29/40117 (2019.08); H10B 41/41 (2023.02); H10B 43/40 (2023.02)] | 20 Claims |
1. A memory device, comprising:
a first bottom-select-gate (BSG) structure, comprising cut slits extending vertically through the first BSG structure;
a cell-layers structure on the first BSG structure; and
gate-line slits extending vertically through the cell-layers structure and the first BSG structure and arranged along a lateral direction to distinguish a plurality of regions in a block of the memory device, wherein:
the gate-line slits comprise a first gate-line slit between first and second regions of the plurality of regions, the first gate-line slit including gate-line sub-slits, and
the cut slits comprise a first cut-slit in the second region and connecting to a gate-line sub-slit of the first gate-line slit to define a first BSG in a first portion of the second region, wherein:
the first BSG in the first portion of the second region is electrically connected to cell strings in the first region through an inter portion between the gate-line sub-slit and an adjacent gate-line sub-slit of the first gate-line slit.
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