US 11,749,735 B2
Method for forming shielding polysilicon sidewall for protecting shielded gate trench metal-oxide-semiconductor field effect transistor
Yi Su, Cupertino, CA (US); and Hong Chang, Saratoga, CA (US)
Assigned to HUAYI MICROELECTRONICS CO., LTD., Xi'an (CN)
Filed by Nanjing Zizhu Microelectronics Co., Ltd., Nanjing (CN)
Filed on Jan. 11, 2021, as Appl. No. 17/146,348.
Prior Publication US 2022/0223703 A1, Jul. 14, 2022
Int. Cl. H01L 29/423 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/4236 (2013.01) [H01L 29/0623 (2013.01); H01L 29/1083 (2013.01); H01L 29/66734 (2013.01); H01L 29/7813 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A method for forming a shielding polysilicon sidewall for protecting a shielded gate trench metal-oxide-semiconductor field effect transistor (SGT MOSFET), comprising:
forming a heavily N-type doped semiconductor substrate with an N-type epitaxial layer to form an semiconductor N-type epitaxial substrate and forming a trench on a surface of the semiconductor N-type epitaxial substrate;
forming a liner oxide layer on an inner wall of the trench;
arranging a heavily N-type doped (>2e20/cm3) shielding polysilicon in the trench, the heavily N-type doped shielding polysilicon not being in contact with the source metal layer;
forming a transition oxide layer on a top and sidewall surface of the heavily N-type doped shielding polysilicon;
removing the liner oxide layer and the transition oxide layer from a top surface of the heavily N-type doped shielding polysilicon, while keeping some remaining transition oxide layer on the sidewall of the heavily N-type doped shielding polysilicon;
forming an inter-polysilicon oxide (IPO) layer on the top surface of the heavily N-type doped shielding polysilicon, the inner wall of the trench; and
forming an N-type doped gate polysilicon above the heavily N-type doped shielding polysilicon, the N-type doped gate polysilicon being isolated from the heavily N-type doped shielding polysilicon through the IPO layer.