CPC H01L 29/41791 (2013.01) [H01L 21/28518 (2013.01); H01L 29/0847 (2013.01); H01L 29/45 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01)] | 20 Claims |
1. A method of manufacturing an integrated circuit device, the method comprising:
forming a fin-type structure that extends in a first direction on a substrate and forming a channel area on the fin-type structure;
forming a gate structure that extends on the substrate in a second direction and that crosses with the fin-type structure;
forming a merged source/drain structure on a side of the gate structure;
forming an etch stop layer on the merged source/drain structure;
partially etching an upper surface of the merged source/drain structure to have a wavy shape by using a residual stop layer as an etch mask;
forming a silicide layer on an etched portion of the merged source/drain structure; and
forming a contact structure electrically connected to the merged source/drain structure and having a bottom surface that corresponds to the wavy shape of the upper surface of the merged source/drain structure.
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