US 11,749,734 B2
Integrated circuit devices and methods of manufacturing the same
Sanghyun Lee, Hwaseong-si (KR); Sungwoo Kang, Suwon-si (KR); Jongchul Park, Seoul (KR); Youngmook Oh, Hwaseong-si (KR); and Jeongyun Lee, Yongin-si (KR)
Assigned to Samsung Electronics Co., Ltd.
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Dec. 23, 2022, as Appl. No. 18/87,854.
Application 18/087,854 is a continuation of application No. 17/329,361, filed on May 25, 2021, granted, now 11,552,176.
Claims priority of application No. 10-2020-0062645 (KR), filed on May 25, 2020.
Prior Publication US 2023/0128547 A1, Apr. 27, 2023
Int. Cl. H01L 29/78 (2006.01); H01L 29/417 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 21/285 (2006.01); H01L 29/45 (2006.01)
CPC H01L 29/41791 (2013.01) [H01L 21/28518 (2013.01); H01L 29/0847 (2013.01); H01L 29/45 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing an integrated circuit device, the method comprising:
forming a fin-type structure that extends in a first direction on a substrate and forming a channel area on the fin-type structure;
forming a gate structure that extends on the substrate in a second direction and that crosses with the fin-type structure;
forming a merged source/drain structure on a side of the gate structure;
forming an etch stop layer on the merged source/drain structure;
partially etching an upper surface of the merged source/drain structure to have a wavy shape by using a residual stop layer as an etch mask;
forming a silicide layer on an etched portion of the merged source/drain structure; and
forming a contact structure electrically connected to the merged source/drain structure and having a bottom surface that corresponds to the wavy shape of the upper surface of the merged source/drain structure.