US 11,749,731 B2
Semiconductor device
Susumu Yamada, Kariya (JP); Satoru Sugita, Kariya (JP); and Kenji Komiya, Kariya (JP)
Assigned to DENSO CORPORATION, Kariya (JP)
Filed by DENSO CORPORATION, Kariya (JP)
Filed on Aug. 4, 2021, as Appl. No. 17/394,278.
Application 17/394,278 is a continuation of application No. PCT/JP2020/000817, filed on Jan. 14, 2020.
Claims priority of application No. 2019-023694 (JP), filed on Feb. 13, 2019.
Prior Publication US 2021/0367048 A1, Nov. 25, 2021
Int. Cl. H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 23/34 (2006.01); H01L 23/495 (2006.01); H01L 23/00 (2006.01); H01L 29/06 (2006.01)
CPC H01L 29/41775 (2013.01) [H01L 29/4238 (2013.01); H01L 23/34 (2013.01); H01L 23/4951 (2013.01); H01L 23/49562 (2013.01); H01L 23/49568 (2013.01); H01L 24/33 (2013.01); H01L 24/73 (2013.01); H01L 29/0696 (2013.01); H01L 29/41741 (2013.01); H01L 2224/33181 (2013.01); H01L 2224/73215 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/10272 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a semiconductor chip having a front surface and a back surface opposite to the front surface;
a first conductive member disposed adjacent to the back surface of the semiconductor chip; and
a second conductive member disposed adjacent to the front surface of the semiconductor chip, wherein
the semiconductor chip includes:
a semiconductor substrate having a plurality of active regions formed with elements, and an inactive region not formed with an element, the inactive region including an inter-inactive portion disposed between at least two active regions and an outer peripheral inactive portion disposed on an outer periphery of the at least two active regions;
a surface electrode disposed to continuously extend above the at least two active regions and the inter-inactive portion; and
a plurality of gate wirings disposed above the inactive region adjacent to the front surface, the plurality of gate wirings including a first gate wiring disposed on an outer periphery of the surface electrode, and a second gate electrode disposed at a position facing the surface electrode, and
the first gate wiring includes a polysilicon wiring and a metal wiring, and
the second gate wiring includes a polysilicon wiring without having a metal wiring.