US 11,749,722 B2
Semiconductor device
Takuma Suzuki, Himeji Hyogo (JP); Sozo Kanie, Himeji Hyogo (JP); Chiharu Ota, Kawasaki Kanagawa (JP); Susumu Obata, Yokokama Kanagawa (JP); and Kazuhisa Goto, Yokohama Kanagawa (JP)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (JP); and Toshiba Electronic Devices & Storage Corporation, Tokyo (JP)
Filed by Kabushiki Kaisha Toshiba, Tokyo (JP); and Toshiba Electronic Devices & Storage Corporation, Tokyo (JP)
Filed on Jul. 16, 2021, as Appl. No. 17/377,955.
Claims priority of application No. 2020-122515 (JP), filed on Jul. 17, 2020.
Prior Publication US 2022/0020853 A1, Jan. 20, 2022
Int. Cl. H01L 29/16 (2006.01); H01L 29/78 (2006.01); H01L 29/32 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/1608 (2013.01) [H01L 29/32 (2013.01); H01L 29/66068 (2013.01); H01L 29/7802 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a silicon carbide layer having a first face and a second face facing the first face and including:
a first silicon carbide region of a first conductive type;
a second silicon carbide region of a second conductive type disposed between the first silicon carbide region and the first face;
a third silicon carbide region of a second conductive type disposed between the first silicon carbide region and the first face, the first silicon carbide region being interposed between the second silicon carbide region and the third silicon carbide region;
a fourth silicon carbide region of a first conductive type disposed between the second silicon carbide region and the first face;
a fifth silicon carbide region of a first conductive type disposed between the third silicon carbide region and the first face;
a sixth silicon carbide region of a second conductive type disposed between the first silicon carbide region and the first face and disposed between the second silicon carbide region and the third silicon carbide region; and
a crystal defect, at least a part of the crystal defect being disposed in the sixth silicon carbide region;
a gate electrode disposed on a side of the first face of the silicon carbide layer;
a gate insulating layer disposed between the second silicon carbide region and the gate electrode, between the third silicon carbide region and the gate electrode, and between the sixth silicon carbide region and the gate electrode;
a first electrode disposed on a side of the first face of the silicon carbide layer; and
a second electrode disposed on a side of the second face of the silicon carbide layer.