US 11,749,715 B2
Isolation regions in integrated circuit structures
Guillaume Bouche, Portland, OR (US); Sean T. Ma, Portland, OR (US); and Andy Chih-Hung Wei, Yamhill, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 6, 2022, as Appl. No. 17/714,182.
Application 17/714,182 is a continuation of application No. 16/829,590, filed on Mar. 25, 2020, granted, now 11,342,409.
Prior Publication US 2022/0231121 A1, Jul. 21, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/06 (2006.01); H01L 27/088 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/0619 (2013.01) [H01L 27/0886 (2013.01); H01L 29/42392 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) component, comprising:
a first region comprising semiconductor materials, the first region including first layers alternating with second layers, individual ones of the first layers comprising a different semiconductor material from individual ones of the second layers; and
a second region comprising semiconductor materials, the second region including third layers alternating with fourth layers, individual ones of the third layers comprising a different semiconductor material from individual ones of the fourth layers,
wherein individual ones of the third layers and the fourth layers are thicker than individual ones of the first layers and the second layers.