US 11,749,714 B2
Capacitor including perovskite material, semiconductor device including the capacitor, and method of manufacturing the capacitor
Jeongil Bang, Suwon-si (KR); Seungwoo Jang, Suwon-si (KR); Hyosik Mun, Hwaseong-si (KR); Younggeun Park, Suwon-si (KR); and Jooho Lee, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jun. 29, 2022, as Appl. No. 17/853,290.
Application 17/853,290 is a division of application No. 17/096,239, filed on Nov. 12, 2020, granted, now 11,417,724.
Claims priority of application No. 10-2020-0084344 (KR), filed on Jul. 8, 2020.
Prior Publication US 2022/0328616 A1, Oct. 13, 2022
Int. Cl. H01L 21/00 (2006.01); H01L 49/02 (2006.01); H10B 53/30 (2023.01); H01L 21/02 (2006.01)
CPC H01L 28/60 (2013.01) [H01L 28/56 (2013.01); H10B 53/30 (2023.02); H01L 21/02197 (2013.01); H01L 21/02266 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A method of manufacturing a capacitor, the method comprising:
forming a lower electrode having a perovskite structure;
forming a first dielectric layer, including a perovskite structure, on the lower electrode, the first dielectric layer having a first dielectric constant and a first band gap energy;
forming a second dielectric layer, including a perovskite structure, on the first dielectric layer, the second dielectric layer having a second dielectric constant less than the first dielectric constant and a second band gap energy greater than the first band gap energy; and
forming an upper electrode having a perovskite structure on the second dielectric layer,
wherein a degree of a lattice mismatch between the lower electrode and the first dielectric layer is about 5% or less and a degree of a lattice mismatch between the lower electrode and the second dielectric layer is about 5% or less,
wherein a ratio of a thickness of the second dielectric layer to a total thickness of the first dielectric layer and the second dielectric layer is about 30% or less, and
wherein the degree of lattice mismatch between the lower electrode and the first dielectric layer is less than the degree of lattice mismatch between the lower electrode and the second dielectric layer.