US 11,749,712 B2
High dielectric constant material at locations of high fields
Dan B. Kasha, Seattle, WA (US); Russell Croman, Buda, TX (US); Stefan N. Mastovich, Round Rock, TX (US); and Thomas C. Fowler, Georgetown, TX (US)
Assigned to Skyworks Solutions, Inc., Irvine, CA (US)
Filed by Skyworks Solutions, Inc., Irvine, CA (US)
Filed on Dec. 20, 2021, as Appl. No. 17/556,258.
Application 17/556,258 is a continuation of application No. 16/726,477, filed on Dec. 24, 2019, granted, now 11,205,696.
Prior Publication US 2022/0115497 A1, Apr. 14, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/00 (2006.01); H01L 49/02 (2006.01)
CPC H01L 28/60 (2013.01) [H01L 24/48 (2013.01); H01L 24/85 (2013.01); H01L 2224/48265 (2013.01); H01L 2924/19104 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a bottom conductive plate;
a top conductive plate;
a first dielectric region formed from a first dielectric material, a first portion of the first dielectric region being between the top conductive plate and the bottom conductive plate;
a second dielectric region that includes a second dielectric material having a higher dielectric constant than the first dielectric material, the second dielectric region having an inner portion below a portion of the top conductive plate and an outer portion extending beyond an edge of the top conductive plate; and
a third dielectric region that includes the second dielectric material, the third dielectric region having an inner portion above a portion of the bottom conductive plate and an outer portion extending beyond an outer edge of the bottom conductive plate.
 
9. A method of making an integrated circuit comprising:
forming a bottom conductive plate;
forming a first dielectric region of at least a first dielectric material, a first portion of the first dielectric region being formed above the bottom conductive plate;
forming a second dielectric region having an inner perimeter and an outer perimeter, the second dielectric region being formed above the first portion of the first dielectric region, the second dielectric region including at least a second dielectric material, the second dielectric material having a higher dielectric constant than the first dielectric material; and
forming a top conductive plate such that an outer portion of the second dielectric region extends beyond an edge of the top conductive plate and an inner portion of the top conductive plate is above and adjacent to an inner portion of the second dielectric region; and
forming a third dielectric region that includes the second dielectric material, the third dielectric region having a second inner perimeter and a second outer perimeter, a portion of a bottom surface of the third dielectric region being formed adjacent to a top surface of the bottom conductive plate.
 
16. A method of making an integrated circuit comprising:
forming a bottom conductive plate;
forming a first dielectric region of at least a first dielectric material, a first portion of the first dielectric region being formed above the bottom conductive plate;
forming a second dielectric region having an inner perimeter and an outer perimeter, the second dielectric region being formed above the first portion of the first dielectric region, the second dielectric region including at least a second dielectric material, the second dielectric material having a higher dielectric constant than the first dielectric material; and
forming a top conductive plate such that an outer portion of the second dielectric region extends beyond an edge of the top conductive plate and an inner portion of the top conductive plate is above and adjacent to an inner portion of the second dielectric region;
forming a layer that includes the second dielectric material above the first dielectric region;
removing a first portion of the layer to form the second dielectric region; and
forming the top conductive plate with a portion of the top conductive plate being formed in a region where the first portion of the layer was removed.