CPC H01L 27/0922 (2013.01) [H01L 21/02178 (2013.01); H01L 27/0924 (2013.01); H01L 29/0665 (2013.01); H01L 29/66666 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7827 (2013.01)] | 20 Claims |
1. A method of fabricating a plurality of field effect transistor devices, comprising:
forming conversion layer segments on a gate dielectric layer on a subset of a plurality of semiconductor device channels;
forming a capping layer on each of the plurality of semiconductor device channels; and
heat treating the conversion layer segments and plurality of semiconductor device channels to form a dipole layer between an interfacial layer on the plurality of semiconductor device channels and gate dielectric layer on the subset of the plurality of semiconductor device channels.
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