US 11,749,649 B2
Composite IC chips including a chiplet embedded within metallization layers of a host IC chip
Adel Elsherbini, Tempe, AZ (US); Johanna Swan, Scottsdale, AZ (US); Shawna Liff, Scottsdale, AZ (US); Patrick Morrow, Portland, OR (US); Gerald Pasdast, San Jose, CA (US); and Van Le, Beaverton, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Aug. 11, 2021, as Appl. No. 17/399,185.
Application 17/399,185 is a continuation of application No. 16/586,145, filed on Sep. 27, 2019, granted, now 11,094,672.
Prior Publication US 2021/0375830 A1, Dec. 2, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 25/065 (2023.01); H01L 23/538 (2006.01); H01L 23/522 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 23/5226 (2013.01); H01L 23/5389 (2013.01); H01L 24/08 (2013.01); H01L 24/09 (2013.01); H01L 25/50 (2013.01); H01L 2224/08146 (2013.01); H01L 2224/0912 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) device structure, comprising:
a first IC chip comprising a first device layer and a first metallization layer interconnected to transistors of the first device layer;
a second IC chip over a first region of the first IC chip, the second IC chip comprising a second device layer and a second metallization layer interconnected to transistors of the second device layer; and
a third metallization layer over a second region of the first IC chip, and adjacent to an edge of the second IC chip, the third metallization layer interconnected to transistors of at least one of the first or second device layers.