US 11,749,642 B2
Microelectronic assemblies with communication networks
Adel A. Elsherbini, Tempe, AZ (US); Amr Elshazly, Hillsboro, OR (US); Arun Chandrasekhar, Chandler, AZ (US); Shawna M. Liff, Scottsdale, AZ (US); and Johanna M. Swan, Scottsdale, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 28, 2022, as Appl. No. 17/706,156.
Application 17/706,156 is a continuation of application No. 17/128,558, filed on Dec. 21, 2020, granted, now 11,437,348.
Application 17/128,558 is a continuation of application No. 16/648,464, granted, now 11,342,305, previously published as PCT/US2017/068917, filed on Dec. 29, 2017.
Prior Publication US 2022/0216182 A1, Jul. 7, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/48 (2006.01); H01L 25/065 (2023.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/0652 (2013.01) [H01L 23/49822 (2013.01); H01L 25/50 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A microelectronic assembly, comprising:
a package substrate;
a plurality of first dies; and
a plurality of second dies, wherein at least one of the second dies is coupled to at least two of the first dies with first interconnects, and at least one of the second dies is coupled to the package substrate with second interconnects, wherein the first interconnects include:
a first set of conductive contacts on the at least one of the second dies that is coupled to the at least two of the first dies, the first set of conductive contacts bonded with conductive contacts on a first one of the least two of the first dies, and a second set of conductive contacts on the at least one of the second dies that is coupled to the at least two of the first dies, the second set of conductive contacts bonded with conductive contacts on a second one of the least two of the first dies.