US 11,749,622 B2
Field effect transistor and semiconductor device
Chihoko Akiyama, Yokohama (JP)
Assigned to SUMITOMO DEVICE INNOVATIONS, INC., Kanagawa (JP)
Filed by SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC., Kanagawa (JP)
Filed on Jun. 30, 2021, as Appl. No. 17/363,446.
Application 17/363,446 is a continuation of application No. 16/801,477, filed on Feb. 26, 2020, granted, now 11,081,452.
Claims priority of application No. 2019-035726 (JP), filed on Feb. 28, 2019.
Prior Publication US 2021/0327827 A1, Oct. 21, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/58 (2006.01); H01L 23/00 (2006.01); H01L 23/492 (2006.01); H01L 29/06 (2006.01); H01L 29/20 (2006.01); H01L 29/778 (2006.01); H01L 29/423 (2006.01); H01L 29/47 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 21/311 (2006.01); H01L 29/205 (2006.01); H01L 29/45 (2006.01); H01L 21/3213 (2006.01); H01L 21/027 (2006.01)
CPC H01L 23/585 (2013.01) [H01L 23/492 (2013.01); H01L 23/564 (2013.01); H01L 24/05 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 29/0684 (2013.01); H01L 21/0217 (2013.01); H01L 21/0254 (2013.01); H01L 21/0272 (2013.01); H01L 21/0277 (2013.01); H01L 21/02211 (2013.01); H01L 21/02274 (2013.01); H01L 21/2654 (2013.01); H01L 21/31144 (2013.01); H01L 21/32139 (2013.01); H01L 24/03 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/402 (2013.01); H01L 29/42316 (2013.01); H01L 29/452 (2013.01); H01L 29/475 (2013.01); H01L 29/66462 (2013.01); H01L 29/7786 (2013.01); H01L 2224/0345 (2013.01); H01L 2224/0346 (2013.01); H01L 2224/03614 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05582 (2013.01); H01L 2224/05644 (2013.01); H01L 2224/05666 (2013.01); H01L 2224/05684 (2013.01); H01L 2224/29139 (2013.01); H01L 2224/29144 (2013.01); H01L 2224/29147 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/1033 (2013.01); H01L 2924/10344 (2013.01); H01L 2924/13064 (2013.01); H01L 2924/30111 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A field effect transistor comprising:
a substrate including a main surface and a back surface;
a semiconductor region on the main surface, the semiconductor region including an inactive region and an active region;
a gate electrode, a source electrode, and a drain electrode on the active region;
a drain pad being on the inactive region and electrically connected to the drain electrode; and
a drain guard on and in contact with the inactive region of the semiconductor region, the drain guard being apart from the drain pad,
wherein the drain guard is in a non-conductive state with respect to the gate electrode, the source electrode and the drain electrode.