CPC H01L 21/823412 (2013.01) [H01L 21/0259 (2013.01); H01L 21/02603 (2013.01); H01L 21/31111 (2013.01); H01L 21/823431 (2013.01); H01L 21/823468 (2013.01); H01L 27/088 (2013.01); H01L 27/0886 (2013.01); H01L 29/0665 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/66742 (2013.01); H01L 29/785 (2013.01); H01L 29/78696 (2013.01)] | 20 Claims |
1. A method, comprising:
forming an inter-sheet filler layer between first semiconductor nanostructures of a first nanostructure transistor and between second semiconductor nanostructures of a second nanostructure transistor;
removing the inter-sheet filler layer from between the first semiconductor nanostructures;
forming a first gate metal layer between the first semiconductor nanostructures and on the second semiconductor nanostructures while the inter-sheet filler layer is between the second semiconductor nanostructures;
removing the first gate metal layer and the inter-sheet filler layer from the second semiconductor nanostructures; and
forming a second gate metal layer between the second semiconductor nanostructures and on the first gate metal layer over the first semiconductor nanostructures.
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