US 11,749,566 B2
Inner filler layer for multi-patterned metal gate for nanostructure transistor
Shahaji B. More, Hsinchu (TW); and Chandrashekhar Prakash Savant, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 10, 2021, as Appl. No. 17/316,486.
Claims priority of provisional application 63/138,270, filed on Jan. 15, 2021.
Prior Publication US 2022/0230923 A1, Jul. 21, 2022
Int. Cl. H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 21/311 (2006.01); H01L 21/02 (2006.01); H01L 29/78 (2006.01)
CPC H01L 21/823412 (2013.01) [H01L 21/0259 (2013.01); H01L 21/02603 (2013.01); H01L 21/31111 (2013.01); H01L 21/823431 (2013.01); H01L 21/823468 (2013.01); H01L 27/088 (2013.01); H01L 27/0886 (2013.01); H01L 29/0665 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/66742 (2013.01); H01L 29/785 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming an inter-sheet filler layer between first semiconductor nanostructures of a first nanostructure transistor and between second semiconductor nanostructures of a second nanostructure transistor;
removing the inter-sheet filler layer from between the first semiconductor nanostructures;
forming a first gate metal layer between the first semiconductor nanostructures and on the second semiconductor nanostructures while the inter-sheet filler layer is between the second semiconductor nanostructures;
removing the first gate metal layer and the inter-sheet filler layer from the second semiconductor nanostructures; and
forming a second gate metal layer between the second semiconductor nanostructures and on the first gate metal layer over the first semiconductor nanostructures.