CPC G11C 29/38 (2013.01) [G11C 29/4401 (2013.01)] | 23 Claims |
1. A memory controller, comprising:
a test circuit suitable for generating a test command, a test address, and test data during a test operation;
a refresh control circuit suitable for receiving the test command and the test address as an active command and an active address, and generating a first target address based on a priority address generated by counting a number of inputs of a partial address corresponding to some bits of the active address and a plurality of primary sampling addresses generated by sampling the active address according to the active command, during the test operation;
a command/address generator suitable for providing the active address together with the active command, and providing a first target refresh command together with the first target address to a memory device, while determining whether to repair the active address according to a repair control signal; and
a repair analysis circuit suitable for generating the repair control signal based on a comparison result of the test data and read data from the memory device, during the test operation.
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