US 11,749,371 B2
Memory system including memory device performing target refresh
Woongrae Kim, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Oct. 26, 2021, as Appl. No. 17/511,222.
Claims priority of provisional application 63/125,053, filed on Dec. 14, 2020.
Claims priority of application No. 10-2021-0116936 (KR), filed on Sep. 2, 2021.
Prior Publication US 2022/0189573 A1, Jun. 16, 2022
Int. Cl. G11C 29/38 (2006.01); G11C 29/44 (2006.01)
CPC G11C 29/38 (2013.01) [G11C 29/4401 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A memory controller, comprising:
a test circuit suitable for generating a test command, a test address, and test data during a test operation;
a refresh control circuit suitable for receiving the test command and the test address as an active command and an active address, and generating a first target address based on a priority address generated by counting a number of inputs of a partial address corresponding to some bits of the active address and a plurality of primary sampling addresses generated by sampling the active address according to the active command, during the test operation;
a command/address generator suitable for providing the active address together with the active command, and providing a first target refresh command together with the first target address to a memory device, while determining whether to repair the active address according to a repair control signal; and
a repair analysis circuit suitable for generating the repair control signal based on a comparison result of the test data and read data from the memory device, during the test operation.