US 11,749,367 B2
Circuit and method for capturing and transporting data errors
Vivek Mohan Sharma, New Delhi (IN); Deepak Baranwal, Greater Noida (IN); Nicolas Bernard Grossier, Oreno di Vimercate (IT); and Samiksha Agarwal, New Delhi (IN)
Assigned to STMICROELECTRONICS INTERNATIONAL N.V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on Jan. 3, 2022, as Appl. No. 17/567,481.
Application 17/567,481 is a continuation of application No. 17/010,272, filed on Sep. 2, 2020, granted, now 11,217,323.
Prior Publication US 2022/0122682 A1, Apr. 21, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/06 (2006.01); G11C 29/10 (2006.01); G11C 29/44 (2006.01); G06F 13/16 (2006.01); G11C 29/42 (2006.01)
CPC G11C 29/10 (2013.01) [G06F 13/1605 (2013.01); G06F 13/1689 (2013.01); G11C 29/42 (2013.01); G11C 29/44 (2013.01); G11C 2029/4402 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A method comprising:
receiving, with a first buffer of a first error compactor unit (ECU) circuit, a first error packet associated with a first circuit;
receiving, with the first buffer, a second error packet associated with a second circuit;
transmitting a first reading request for reading the first error packet;
receiving the first reading request with an arbiter circuit of an error aggregator unit (EAU) circuit of a central error management circuit;
in response to receiving the first reading request, reading the first error packet from the first buffer, transmitting the first error packet to a controller of the central error management circuit, and transmitting a first acknowledgement to the first ECU circuit;
receiving the first acknowledgement with the first ECU circuit; and
in response to receiving the first acknowledgement, transmitting a second reading request for reading the second error packet.