US 11,749,366 B2
Semiconductor memory device capable of performing soft-post-package-repair operation
Yasushi Matsubara, Isehara (JP); Alan Wilson, Boise, ID (US); and Minoru Someya, Chofu (JP)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Jan. 18, 2022, as Appl. No. 17/578,305.
Prior Publication US 2023/0230648 A1, Jul. 20, 2023
Int. Cl. G11C 29/02 (2006.01); G11C 29/44 (2006.01); G11C 29/12 (2006.01); G11C 7/10 (2006.01); G11C 29/18 (2006.01); G11C 8/18 (2006.01)
CPC G11C 29/027 (2013.01) [G11C 7/1012 (2013.01); G11C 8/18 (2013.01); G11C 29/1201 (2013.01); G11C 29/12015 (2013.01); G11C 29/18 (2013.01); G11C 29/4401 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a fuse array circuit including a plurality of fuse sets each assigned to a corresponding one of a plurality of fuse addresses and configured to operatively store a fuse data:
a first circuit configured to generate and sequentially update a fuse address to sequentially read the fuse data from the plurality of fuse sets; and
a second circuit configured to generate the first signal based on the fuse address generated by the first circuit,
wherein the first circuit is configured to change a frequency of updating the fuse address based on a first signal,
wherein the second circuit is configured to bring the first signal into a first state when the fuse address generated by the first circuit is in a first address range,
wherein the second circuit is configured to bring the first signal into a second state when the fuse address generated by the first circuit is in a second address range,
wherein the first circuit is configured to update the fuse address at a first frequency when the first signal is in the first state, and
wherein the first circuit is configured to update the fuse address at a second frequency lower than the first frequency when the first signal is in the second state.